Module: vout_7seg

Child-Modules

Source

2 module vout_7seg (
3         input clk,
4         input signed [31:0] value,
5         output reg en1,
6         output reg en2,
7         output reg en3,
8         output reg en4,
9         output wire displayA,
10         output wire displayB,
11         output wire displayC,
12         output wire displayD,
13         output wire displayE,
14         output wire displayF,
15         output wire displayG
16     );
17 
18 
19     wire [6:0] display;
20     assign displayA = display[0];
21     assign displayB = display[1];
22     assign displayC = display[2];
23     assign displayD = display[3];
24     assign displayE = display[4];
25     assign displayF = display[5];
26     assign displayG = display[6];
27 
28     wire [19:0] bcd;
29 
30     bin2bcd bin2bcd1 (
31         .bin (value[15:0]),
32         .bcd (bcd)
33     );
34     wire [7:0] int1;
35     wire [7:0] int10;
36     wire [7:0] int100;
37     wire [7:0] int1000;
38     wire [7:0] int10000;
39     assign int1 = 8'd48 + {4'd0, bcd[3:0]};
40     assign int10 = 8'd48 + {4'd0, bcd[7:4]};
41     assign int100 = 8'd48 + {4'd0, bcd[11:8]};
42     assign int1000 = 8'd48 + {4'd0, bcd[15:12]};
43     assign int10000 = 8'd48 + {4'd0, bcd[19:16]};
44 
45     reg [3:0] digit;
46 
47     reg [7:0] digit_delay = 0;
48     reg [1:0] digit_n = 0;
49     always @(posedge clk) begin
50     
51         digit_delay <= digit_delay + 1;
52 
53         if (digit_delay == 0) begin
54             digit_n <= digit_n + 1;
55         end
56  
57 		case (digit_n)
58 			2'h0: begin
59                 digit <= int1;
60                 en1 <= 0;
61                 en2 <= 1;
62                 en3 <= 1;
63                 en4 <= 1;
64             end
65 			2'h1: begin
66                 digit <= int10;
67                 en1 <= 1;
68                 en2 <= 0;
69                 en3 <= 1;
70                 en4 <= 1;
71             end
72 			2'h2: begin
73                 digit <= int100;
74                 en1 <= 1;
75                 en2 <= 1;
76                 en3 <= 0;
77                 en4 <= 1;
78             end
79 			2'h3: begin
80                 digit <= int1000;
81                 en1 <= 1;
82                 en2 <= 1;
83                 en3 <= 1;
84                 en4 <= 0;
85             end
86 		endcase
87 
88     end
89 
90 
91     seven_segments ss1 (
92         .clk(clk),
93         .binary(digit),
94         .display(display)
95     );
96 
97 endmodule