Module: uart_baud
Ports:
|
| Direction | Size | Name |
|---|
| input | | clk |
| input | | enable |
| output | | tick |
Parameter:
|
| Parameter | Default |
|---|
| Baud | 0xF4240 | 1000000 |
| ClkFrequency | 0x2DC6C00 | 48000000 |
| Oversampling | 0x1 | 1 |
Child-Modules
Source
Filename: uart_baud.v
4 module uart_baud(
5 input clk, enable,
6 output tick // generate a tick at the specified baud rate * oversampling
7 );
8 parameter ClkFrequency = 12000000;
9 parameter Baud = 2000000;
10 parameter Oversampling = 1;
11
12 function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
13 localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
14 reg [AccWidth:0] Acc = 0;
15 localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
16 localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
17 always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
18 assign tick = Acc[AccWidth];
19 endmodule