Module: rio

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Child-Modules

blink1: blink
uart1: interface_uart
vin_ir5: vin_ir
vin_ps26: vin_ps2
vin_tlc549c7: vin_tlc549c
vout_7seg8: vout_7seg
vout_frequency4: vout_frequency

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Source

Filename: rio.v

12 module rio (
13         output BLINK_LED,
14         input SW_S1,
15         input SW_S2,
16         input SW_S3,
17         input SW_S4,
18         input INTERFACE_UART_RX,
19         output INTERFACE_UART_TX,
20         input sysclk,
21         input VIN5_IR,
22         input VIN6_CLK,
23         input VIN6_DATA,
24         input VIN7_MISO,
25         output VIN7_SCLK,
26         output VIN7_CS,
27         output VOUT8_7SEG_EN1,
28         output VOUT8_7SEG_EN2,
29         output VOUT8_7SEG_EN3,
30         output VOUT8_7SEG_EN4,
31         output VOUT8_7SEG_SEG_A,
32         output VOUT8_7SEG_SEG_B,
33         output VOUT8_7SEG_SEG_C,
34         output VOUT8_7SEG_SEG_D,
35         output VOUT8_7SEG_SEG_E,
36         output VOUT8_7SEG_SEG_F,
37         output VOUT8_7SEG_SEG_G,
38         output VOUT4_FREQUENCY
39     );
40 
41 
42     reg ESTOP = 0;
43     wire ERROR;
44     wire INTERFACE_TIMEOUT;
45     assign ERROR = (INTERFACE_TIMEOUT | ESTOP);
46     blink #(24000000) blink1 (
47         .clk (sysclk),
48         .led (BLINK_LED)
49     );
50 
51     parameter BUFFER_SIZE = 136;
52 
53     wire[135:0] rx_data;
54     wire[135:0] tx_data;
55 
56     reg signed [31:0] header_tx;
57     always @(posedge sysclk) begin
58         if (ESTOP) begin
59             header_tx <= 32'h65737470;
60         end else begin
61             header_tx <= 32'h64617461;
62         end
63     end
64 
65     // vouts 2
66     wire signed [31:0] SP8;
67     wire signed [31:0] SOUND;
68 
69     // vins 3
70     wire signed [31:0] PV6;
71     wire signed [31:0] PV7;
72     wire signed [31:0] PV5;
73 
74     // rx_data 104
75     wire [31:0] header_rx;
76     assign header_rx = {rx_data[111:104], rx_data[119:112], rx_data[127:120], rx_data[135:128]};
77     assign SP8 = {rx_data[79:72], rx_data[87:80], rx_data[95:88], rx_data[103:96]};
78     assign SOUND = {rx_data[47:40], rx_data[55:48], rx_data[63:56], rx_data[71:64]};
79     // assign DOUTx = rx_data[39];
80     // assign DOUTx = rx_data[38];
81     // assign DOUTx = rx_data[37];
82     // assign DOUTx = rx_data[36];
83     // assign DOUTx = rx_data[35];
84     // assign DOUTx = rx_data[34];
85     // assign DOUTx = rx_data[33];
86     // assign DOUTx = rx_data[32];
87     // tx_data 136
88     assign tx_data = {
89         header_tx[7:0], header_tx[15:8], header_tx[23:16], header_tx[31:24],
90         PV6[7:0], PV6[15:8], PV6[23:16], PV6[31:24],
91         PV7[7:0], PV7[15:8], PV7[23:16], PV7[31:24],
92         PV5[7:0], PV5[15:8], PV5[23:16], PV5[31:24],
93         ~SW_S1, ~SW_S2, ~SW_S3, ~SW_S4, 1'd0, 1'd0, 1'd0, 1'd0
94     };
95 
96     // vin_ps2
97     vin_ps2 #(24) vin_ps26 (
98         .clk (sysclk),
99         .code (PV6),
100         .ps2_clk (VIN6_CLK),
101         .ps2_data (VIN6_DATA)
102     );
103 
104     // vin_tlc549c
105     vin_tlc549c #(24) vin_tlc549c7 (
106         .clk (sysclk),
107         .adc_data (PV7),
108         .adc_data_in (VIN7_MISO),
109         .adc_clk (VIN7_SCLK),
110         .adc_cs_n (VIN7_CS)
111     );
112 
113     // vout_7seg
114     vout_7seg vout_7seg8 (
115         .clk (sysclk),
116         .value (SP8),
117         .en1 (VOUT8_7SEG_EN1),
118         .en2 (VOUT8_7SEG_EN2),
119         .en3 (VOUT8_7SEG_EN3),
120         .en4 (VOUT8_7SEG_EN4),
121         .displayA (VOUT8_7SEG_SEG_A),
122         .displayB (VOUT8_7SEG_SEG_B),
123         .displayC (VOUT8_7SEG_SEG_C),
124         .displayD (VOUT8_7SEG_SEG_D),
125         .displayE (VOUT8_7SEG_SEG_E),
126         .displayF (VOUT8_7SEG_SEG_F),
127         .displayG (VOUT8_7SEG_SEG_G)
128     );
129 
130     // vout_frequency
131     vout_frequency vout_frequency4 (
132         .clk (sysclk),
133         .frequency (SOUND),
134         .disabled (ERROR),
135         .SIGNAL (VOUT4_FREQUENCY)
136     );
137 
138     // interface_uart
139     assign INTERFACE_TIMEOUT = 0;
140     interface_uart #(BUFFER_SIZE, 32'h74697277, 32'd12000000, 48000000, 1000000) uart1 (
141         .clk (sysclk),
142         .UART_RX (INTERFACE_UART_RX),
143         .UART_TX (INTERFACE_UART_TX),
144         .rx_data (rx_data),
145         .tx_data (tx_data)
146     );
147 
148     // vin_ir
149     vin_ir #(24) vin_ir5 (
150         .clk (sysclk),
151         .Code (PV5),
152         .ir (VIN5_IR)
153     );
154 endmodule

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