Module: seven_segments
Ports:
|
| Direction | Size | Name |
|---|
| input | [3:0] | binary |
| input | | clk |
| output | [6:0] | display |
Child-Modules
Source
Filename: vout_7seg.v
120 module seven_segments (
121 input wire clk,
122 input wire [3:0] binary,
123 output reg [6:0] display
124 );
125
126 always @(binary) begin
127 case (binary)
128 4'h0: display = 7'b0111111;
129 4'h1: display = 7'b0000110;
130 4'h2: display = 7'b1011011;
131 4'h3: display = 7'b1001111;
132 4'h4: display = 7'b1100110;
133 4'h5: display = 7'b1101101;
134 4'h6: display = 7'b1111101;
135 4'h7: display = 7'b0000111;
136 4'h8: display = 7'b1111111;
137 4'h9: display = 7'b1101111;
138
139 4'ha: display = 7'b1110111;
140 4'hb: display = 7'b1111100;
141 4'hc: display = 7'b0111001;
142 4'hd: display = 7'b1011110;
143 4'he: display = 7'b1111001;
144 4'hf: display = 7'b1110001;
145 default: display = 7'b1111001;
146 endcase
147 end
148
149 endmodule