Module: vin_ir
Ports:
|
| Direction | Size | Name |
|---|
| output | [7:0] | Code |
| input | | clk |
| input | | ir |
Parameter:
|
| Parameter | Default |
|---|
| CODE_0 | 0x400 | 1024 |
| CODE_1 | 0x800 | 2048 |
| SPEED | 0x18 | 24 |
| START_H | 0x1000 | 4096 |
| START_L | 0x2000 | 8192 |
| ST_CODE_N | 0x4 | 4 |
| ST_CODE_P | 0x1 | 1 |
| ST_START_H | 0x3 | 3 |
| ST_START_L | 0x0 | 0 |
| ST_VALUE_N | 0x5 | 5 |
| ST_VALUE_P | 0x2 | 2 |
Child-Modules
Source
Filename: vin_ir.v
2 module vin_ir
3 #(parameter SPEED = 24)
4 (
5 input clk,
6 input ir,
7 output reg [7:0]Code
8 );
9
10 reg clk_1us;
11 reg [31:0]counter;
12 always @(posedge clk) begin
13 if (counter == 0) begin
14 counter <= SPEED;
15 clk_1us <= ~clk_1us;
16 end else begin
17 counter <= counter - 1;
18 end
19 end
20
21 reg [2:0]IR_reg;
22 initial IR_reg = 3'b0;
23 always @ (posedge clk_1us)
24 begin
25 IR_reg[0] <= ir;
26 IR_reg[1] <= IR_reg[0];
27 IR_reg[2] <= IR_reg[1];
28 end
29
30 wire IR_pos = (IR_reg[0]==1'b1) & (IR_reg[1]==1'b0);
31 wire IR_pos2= (IR_reg[1]==1'b1) & (IR_reg[2]==1'b0);
32 wire IR_neg = (IR_reg[0]==1'b0) & (IR_reg[1]==1'b1);
33 wire IR_neg2= (IR_reg[1]==1'b0) & (IR_reg[2]==1'b1);
34
35 parameter ST_START_L = 3'b000, ST_CODE_P = 3'b001 , ST_VALUE_P = 3'b010;
36 parameter ST_START_H = 3'b011, ST_CODE_N = 3'b100 , ST_VALUE_N = 3'b101;
37 parameter START_H = 16'd4096;
38 parameter START_L = 16'd8192;
39 parameter CODE_0 = 16'd512 + 16'd512;
40 parameter CODE_1 = 16'd1536 + 16'd512;
41
42 reg [2:0]state;
43 initial state = ST_START_L;
44 reg [15:0]cnt_h;
45 initial cnt_h = 16'b0;
46 reg [15:0]cnt_l;
47 initial cnt_l = 16'b0;
48 reg [31:0]T_Value;
49 initial T_Value = 32'b0;
50
51 reg [31:0]IR_Value;
52 initial IR_Value = 32'b0;
53
54 reg [15:0]cnt_val;
55 initial cnt_val = 16'b0;
56
57 reg Flag_LVL;
58 initial Flag_LVL = 1'b0;
59
60 reg Flag_HVL;
61 initial Flag_HVL = 1'b0;
62
63 always @ (posedge clk_1us or posedge ir) begin
64 if(ir)
65 cnt_l <= 16'b0;
66 else if(cnt_l[15] & cnt_l[10])
67 cnt_l <= 16'b0;
68 else
69 cnt_l <= cnt_l + 1'b1;
70 end
71
72 always @ (negedge clk_1us) begin
73 if(cnt_l == START_L)
74 Flag_LVL <= 1'b1;
75 else if(IR_pos2)
76 Flag_LVL <= 1'b0;
77 end
78
79
80 always @ (posedge clk_1us or negedge ir) begin
81 if(!ir)
82 cnt_h <= 16'b0;
83 else if(cnt_h[15] & cnt_h[10])
84 cnt_h <= 16'b0;
85 else
86 cnt_h <= cnt_h + 1'b1;
87 end
88
89
90 always @ (negedge clk_1us) begin
91 if(cnt_h == START_H)
92 Flag_HVL <=1;
93 else if(IR_neg2)
94 Flag_HVL <= 1'b0;
95 end
96
97 reg [15:0]IR_code;
98 always @ (posedge clk_1us or posedge IR_neg) begin
99 if(IR_neg)
100 begin
101 cnt_val <= 16'b0;
102 end
103 else if(state == ST_CODE_P)
104 begin
105 if(cnt_val == CODE_0)
106 begin
107 IR_code <= CODE_0;
108 cnt_val <= cnt_val + 1'b1;
109 end
110 else if(cnt_val == CODE_1)
111 begin
112 IR_code <= CODE_1;
113 cnt_val <= cnt_val + 1'b1;
114 end
115 else
116 cnt_val <= cnt_val + 1'b1;
117 end
118 end
119
120
121 wire fault = cnt_h[15] | cnt_l[15];
122 reg [5:0]cnt_num;
123 initial cnt_num = 6'b0;
124
125 always @ (posedge clk_1us) begin
126 case(state)
127 ST_START_L: begin
128 cnt_num <= 6'b0;
129 if((IR_pos == 1'b1) & (Flag_LVL==1'b1))
130 begin
131 state <= ST_START_H;
132 end
133 else if(fault)
134 state <= ST_START_L;
135 end
136 ST_START_H: begin
137 cnt_num <= 6'b0;
138 if((IR_neg == 1'b1) & (Flag_HVL==1'b1))
139 begin
140 state <= ST_CODE_P;
141 end
142 else if(fault)
143 state <= ST_START_L;
144 end
145 ST_CODE_P: begin
146 if((IR_neg)&(IR_code == CODE_1))
147 begin
148 cnt_num = cnt_num + 1'b1;
149 IR_Value <= {IR_Value[30:0],1'b1};
150 end
151 else if((IR_neg)&(IR_code == CODE_0))
152 begin
153 cnt_num = cnt_num + 1'b1;
154 IR_Value <= {IR_Value[30:0],1'b0};
155 end
156 else if(cnt_num==6'd32)
157 begin
158 cnt_num <= 6'b0;
159 T_Value <= IR_Value;
160 state <= ST_START_L;
161 Code <= {IR_Value[8],IR_Value[9],IR_Value[10],IR_Value[11],IR_Value[12],IR_Value[13],IR_Value[14],IR_Value[15]};
162 end
163 end
164 default : state <= ST_START_L;
165 endcase
166 end
167
168 endmodule