Module: uart_rx

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Source

4 module uart_rx(
5 	input clk,
6 	input RxD,
7 	output reg RxD_data_ready = 0,
8 	output reg [7:0] RxD_data = 0,  // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
9 	// We also detect if a gap occurs in the received stream of characters
10 	// That can be useful if multiple characters are sent in burst
11 	//  so that multiple characters can be treated as a "packet"
12 	output RxD_idle,  // asserted when no data has been received for a while
13 	output reg RxD_endofpacket = 0  // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
14 );
15 
16     parameter ClkFrequency = 12000000;
17     parameter Baud = 2000000;
18 
19     parameter Oversampling = 8;  // needs to be a power of 2
20     // we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
21     // 8 times oversampling by default, use 16 for higher quality reception
22 
23     reg [3:0] RxD_state = 0;
24 
25     wire OversamplingTick;
26     uart_baud #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
27 
28     // synchronize RxD to our clk domain
29     reg [1:0] RxD_sync = 2'b11;
30     always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
31 
32     // and filter it
33     reg [1:0] Filter_cnt = 2'b11;
34     reg RxD_bit = 1'b1;
35 
36     always @(posedge clk)
37     if(OversamplingTick)
38     begin
39         if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
40         else 
41         if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
42 
43         if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
44         else
45         if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
46     end
47 
48     // and decide when is the good time to sample the RxD line
49     function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
50     localparam l2o = log2(Oversampling);
51     reg [l2o-2:0] OversamplingCnt = 0;
52     always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
53     wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
54 
55     // now we can accumulate the RxD bits in a shift-register
56     always @(posedge clk)
57     case(RxD_state)
58         4'b0000: if(~RxD_bit) RxD_state <= 4'b0001;  // start bit found?
59         4'b0001: if(sampleNow) RxD_state <= 4'b1000;  // sync start bit to sampleNow
60         4'b1000: if(sampleNow) RxD_state <= 4'b1001;  // bit 0
61         4'b1001: if(sampleNow) RxD_state <= 4'b1010;  // bit 1
62         4'b1010: if(sampleNow) RxD_state <= 4'b1011;  // bit 2
63         4'b1011: if(sampleNow) RxD_state <= 4'b1100;  // bit 3
64         4'b1100: if(sampleNow) RxD_state <= 4'b1101;  // bit 4
65         4'b1101: if(sampleNow) RxD_state <= 4'b1110;  // bit 5
66         4'b1110: if(sampleNow) RxD_state <= 4'b1111;  // bit 6
67         4'b1111: if(sampleNow) RxD_state <= 4'b0010;  // bit 7
68         4'b0010: if(sampleNow) RxD_state <= 4'b0000;  // stop bit
69         default: RxD_state <= 4'b0000;
70     endcase
71 
72     always @(posedge clk)
73     if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
74 
75     //reg RxD_data_error = 0;
76     always @(posedge clk)
77     begin
78         RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit);  // make sure a stop bit is received
79         //RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit);  // error if a stop bit is not received
80     end
81 
82     reg [l2o+1:0] GapCnt = 0;
83     always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
84     assign RxD_idle = GapCnt[l2o+1];
85     always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
86 
87 endmodule