Module: vin_ps2

Child-Modules

Source

2 module vin_ps2
3     #(parameter SPEED = 24)
4     (
5         input  clk,
6         input  ps2_clk,
7         input  ps2_data,
8         output reg [15:0]code
9     );
10 
11     reg [7:0] data_curr;
12     reg [7:0] data_pre;
13     reg [3:0] b;
14     reg flag;
15 
16     initial begin
17         b <= 4'h1;
18         flag <= 1'b0;
19         data_curr <= 8'hf0;
20         data_pre <= 8'hf0;
21     end
22 
23     always @(negedge ps2_clk) begin
24         case(b)
25             1: ; //first bit
26             2: data_curr[0] <= ps2_data;
27             3: data_curr[1] <= ps2_data;
28             4: data_curr[2] <= ps2_data;
29             5: data_curr[3] <= ps2_data;
30             6: data_curr[4] <= ps2_data;
31             7: data_curr[5] <= ps2_data;
32             8: data_curr[6] <= ps2_data;
33             9: data_curr[7] <= ps2_data;
34             10: flag <= 1'b1; //Parity bit
35             11: flag <= 1'b0; //Ending bit
36         endcase
37         if (b <= 10) begin
38             b <= b + 1;
39         end else if (b == 11) begin
40             code <= code<<8;
41             code[7:0] <= data_curr;
42             b <= 1;
43         end
44     end
45 
46     always @(posedge flag) begin
47         if (data_curr == 8'hf0) begin
48             //code <= data_pre;
49         end else begin
50             data_pre <= data_curr;
51         end
52     end
53 
54 
55 endmodule