Overview
rio   blink1 (blink)   uart1 (interface_uart)     uart_rx1 (uart_rx)       tickgen (uart_baud)     uart_tx1 (uart_tx)       tickgen (uart_baud)   vin_ir5 (vin_ir)   vin_ps26 (vin_ps2)   vin_tlc549c7 (vin_tlc549c)   vout_7seg8 (vout_7seg)     bin2bcd1 (bin2bcd)     ss1 (seven_segments)   vout_frequency4 (vout_frequency)
rio.v
 rio blink.v
 blink vin_ir.v
 vin_ir interface_uart.v
 interface_uart uart_tx.v
 uart_tx uart_rx.v
 uart_rx uart_baud.v
 uart_baud  uart_baud vout_frequency.v
 vout_frequency vout_7seg.v
 bin2bcd  seven_segments  vout_7seg vin_tlc549c.v
 vin_tlc549c vin_ps2.v
 vin_ps2
G interfaceuart interface_uart PORTS UART_RX UART_TX clk rx_data[135:0] tx_data[135:0] uart_rx1 UART_RX RxD_data RxD_data_ready RxD_endofpacket RxD_idle clk     uart_tx1 UART_TX TxD_busy TxD_data TxD_start clk interface_uart.v uartrx uart_rx PORTS RxD RxD_data[7:0] RxD_data_ready RxD_endofpacket RxD_idle clk tickgen clk $add.B OversamplingTick uart_rx.v interfaceuart:uart_rx1_RxD->uartrx:RxD interfaceuart:uart_rx1_RxD_data->uartrx:RxD_data interfaceuart:uart_rx1_RxD_data_ready->uartrx:RxD_data_ready interfaceuart:uart_rx1_RxD_endofpacket->uartrx:RxD_endofpacket interfaceuart:uart_rx1_RxD_idle->uartrx:RxD_idle interfaceuart:uart_rx1_clk->uartrx:clk uarttx uart_tx PORTS TxD TxD_busy TxD_data[7:0] TxD_start clk tickgen clk TxD_busy BitTick uart_tx.v interfaceuart:uart_tx1_TxD->uarttx:TxD interfaceuart:uart_tx1_TxD_busy->uarttx:TxD_busy interfaceuart:uart_tx1_TxD_data->uarttx:TxD_data interfaceuart:uart_tx1_TxD_start->uarttx:TxD_start interfaceuart:uart_tx1_clk->uarttx:clk uartbaud uart_baud PORTS clk enable tick uart_baud.v uartrx:tickgen_clk->uartbaud:clk uartrx:tickgen_enable->uartbaud:enable uartrx:tickgen_tick->uartbaud:tick uarttx:tickgen_clk->uartbaud:clk uarttx:tickgen_enable->uartbaud:enable uarttx:tickgen_tick->uartbaud:tick blink blink PORTS clk led blink.v vinir vin_ir PORTS Code[7:0] clk ir vin_ir.v vinps2 vin_ps2 PORTS clk code[15:0] ps2_clk ps2_data vin_ps2.v vintlc549c vin_tlc549c PORTS adc_clk adc_cs_n adc_data[7:0] adc_data_in clk vin_tlc549c.v bin2bcd bin2bcd PORTS bcd[19:0] bin[15:0] vout_7seg.v pins PINS output PIN_3 input PIN_87 output PIN_86 input PIN_88 input PIN_91 input PIN_90 input PIN_89 input PIN_132 input PIN_99 input PIN_98 output PIN_129 input PIN_128 output PIN_127 output PIN_85 output PIN_137 output PIN_135 output PIN_136 output PIN_133 output PIN_143 output PIN_144 output PIN_1 output PIN_141 output PIN_142 output PIN_138 output PIN_2 input PIN_24 rio rio PORTS BLINK_LED INTERFACE_UART_RX INTERFACE_UART_TX SW_S1 SW_S2 SW_S3 SW_S4 VIN5_IR VIN6_CLK VIN6_DATA VIN7_CS VIN7_MISO VIN7_SCLK VOUT4_FREQUENCY VOUT8_7SEG_EN1 VOUT8_7SEG_EN2 VOUT8_7SEG_EN3 VOUT8_7SEG_EN4 VOUT8_7SEG_SEG_A VOUT8_7SEG_SEG_B VOUT8_7SEG_SEG_C VOUT8_7SEG_SEG_D VOUT8_7SEG_SEG_E VOUT8_7SEG_SEG_F VOUT8_7SEG_SEG_G sysclk blink1 sysclk BLINK_LED     uart1 INTERFACE_UART_RX INTERFACE_UART_TX sysclk rx_data tx_data     vin_ir5 PV5 sysclk VIN5_IR     vin_ps26 sysclk PV6 VIN6_CLK VIN6_DATA     vin_tlc549c7 VIN7_SCLK VIN7_CS PV7 VIN7_MISO sysclk     vout_7seg8 sysclk VOUT8_7SEG_SEG_A VOUT8_7SEG_SEG_B VOUT8_7SEG_SEG_C VOUT8_7SEG_SEG_D VOUT8_7SEG_SEG_E VOUT8_7SEG_SEG_F VOUT8_7SEG_SEG_G VOUT8_7SEG_EN1 VOUT8_7SEG_EN2 VOUT8_7SEG_EN3 VOUT8_7SEG_EN4 SP8     vout_frequency4 VOUT4_FREQUENCY sysclk INTERFACE_TIMEOUT SOUND rio.v pins:PIN_3->rio:BLINK_LED pins:PIN_87->rio:INTERFACE_UART_RX pins:PIN_86->rio:INTERFACE_UART_TX pins:PIN_88->rio:SW_S1 pins:PIN_91->rio:SW_S2 pins:PIN_90->rio:SW_S3 pins:PIN_89->rio:SW_S4 pins:PIN_132->rio:VIN5_IR pins:PIN_99->rio:VIN6_CLK pins:PIN_98->rio:VIN6_DATA pins:PIN_129->rio:VIN7_CS pins:PIN_128->rio:VIN7_MISO pins:PIN_127->rio:VIN7_SCLK pins:PIN_85->rio:VOUT4_FREQUENCY pins:PIN_137->rio:VOUT8_7SEG_EN1 pins:PIN_135->rio:VOUT8_7SEG_EN2 pins:PIN_136->rio:VOUT8_7SEG_EN3 pins:PIN_133->rio:VOUT8_7SEG_EN4 pins:PIN_143->rio:VOUT8_7SEG_SEG_A pins:PIN_144->rio:VOUT8_7SEG_SEG_B pins:PIN_1->rio:VOUT8_7SEG_SEG_C pins:PIN_141->rio:VOUT8_7SEG_SEG_D pins:PIN_142->rio:VOUT8_7SEG_SEG_E pins:PIN_138->rio:VOUT8_7SEG_SEG_F pins:PIN_2->rio:VOUT8_7SEG_SEG_G pins:PIN_24->rio:sysclk rio:uart1_UART_RX->interfaceuart:UART_RX rio:uart1_UART_TX->interfaceuart:UART_TX rio:uart1_clk->interfaceuart:clk rio:uart1_rx_data->interfaceuart:rx_data rio:uart1_tx_data->interfaceuart:tx_data rio:blink1_clk->blink:clk rio:blink1_led->blink:led rio:vin_ir5_Code->vinir:Code rio:vin_ir5_clk->vinir:clk rio:vin_ir5_ir->vinir:ir rio:vin_ps26_clk->vinps2:clk rio:vin_ps26_code->vinps2:code rio:vin_ps26_ps2_clk->vinps2:ps2_clk rio:vin_ps26_ps2_data->vinps2:ps2_data rio:vin_tlc549c7_adc_clk->vintlc549c:adc_clk rio:vin_tlc549c7_adc_cs_n->vintlc549c:adc_cs_n rio:vin_tlc549c7_adc_data->vintlc549c:adc_data rio:vin_tlc549c7_adc_data_in->vintlc549c:adc_data_in rio:vin_tlc549c7_clk->vintlc549c:clk vout7seg vout_7seg PORTS clk displayA displayB displayC displayD displayE displayF displayG en1 en2 en3 en4 value[31:0] bin2bcd1 bcd value[15:0]     ss1 digit clk display vout_7seg.v rio:vout_7seg8_clk->vout7seg:clk rio:vout_7seg8_displayA->vout7seg:displayA rio:vout_7seg8_displayB->vout7seg:displayB rio:vout_7seg8_displayC->vout7seg:displayC rio:vout_7seg8_displayD->vout7seg:displayD rio:vout_7seg8_displayE->vout7seg:displayE rio:vout_7seg8_displayF->vout7seg:displayF rio:vout_7seg8_displayG->vout7seg:displayG rio:vout_7seg8_en1->vout7seg:en1 rio:vout_7seg8_en2->vout7seg:en2 rio:vout_7seg8_en3->vout7seg:en3 rio:vout_7seg8_en4->vout7seg:en4 rio:vout_7seg8_value->vout7seg:value voutfrequency vout_frequency PORTS SIGNAL clk disabled frequency[31:0] vout_frequency.v rio:vout_frequency4_SIGNAL->voutfrequency:SIGNAL rio:vout_frequency4_clk->voutfrequency:clk rio:vout_frequency4_disabled->voutfrequency:disabled rio:vout_frequency4_frequency->voutfrequency:frequency vout7seg:bin2bcd1_bcd->bin2bcd:bcd vout7seg:bin2bcd1_bin->bin2bcd:bin sevensegments seven_segments PORTS binary[3:0] clk display[6:0] vout_7seg.v vout7seg:ss1_binary->sevensegments:binary vout7seg:ss1_clk->sevensegments:clk vout7seg:ss1_display->sevensegments:display