Module: uart_tx

Child-Modules

Source

4 module uart_tx(
5 	input clk,
6 	input TxD_start,
7 	input [7:0] TxD_data,
8 	output TxD,
9 	output TxD_busy
10 );
11 
12     // Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
13     // TxD_data is latched so that it doesn't have to stay valid while it is being sent
14 
15     parameter ClkFrequency = 12000000;
16     parameter Baud = 2000000;
17 
18     wire BitTick;
19     uart_baud #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
20 
21     reg [3:0] TxD_state = 0;
22     wire TxD_ready = (TxD_state==0);
23     assign TxD_busy = ~TxD_ready;
24 
25     reg [7:0] TxD_shift = 0;
26     always @(posedge clk)
27     begin
28         if(TxD_ready & TxD_start)
29             TxD_shift <= TxD_data;
30         else
31         if(TxD_state[3] & BitTick)
32             TxD_shift <= (TxD_shift >> 1);
33 
34         case(TxD_state)
35             4'b0000: if(TxD_start) TxD_state <= 4'b0100;
36             4'b0100: if(BitTick) TxD_state <= 4'b1000;  // start bit
37             4'b1000: if(BitTick) TxD_state <= 4'b1001;  // bit 0
38             4'b1001: if(BitTick) TxD_state <= 4'b1010;  // bit 1
39             4'b1010: if(BitTick) TxD_state <= 4'b1011;  // bit 2
40             4'b1011: if(BitTick) TxD_state <= 4'b1100;  // bit 3
41             4'b1100: if(BitTick) TxD_state <= 4'b1101;  // bit 4
42             4'b1101: if(BitTick) TxD_state <= 4'b1110;  // bit 5
43             4'b1110: if(BitTick) TxD_state <= 4'b1111;  // bit 6
44             4'b1111: if(BitTick) TxD_state <= 4'b0010;  // bit 7
45             4'b0010: if(BitTick) TxD_state <= 4'b0011;  // stop1
46             4'b0011: if(BitTick) TxD_state <= 4'b0000;  // stop2
47             default: if(BitTick) TxD_state <= 4'b0000;
48         endcase
49     end
50 
51     assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]);  // put together the start, data and stop bits
52 endmodule