Module: vin_tlc549c

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Source

2 module vin_tlc549c
3     #(parameter SPEED = 24)
4     (
5         input		clk,
6         input		adc_data_in,
7         output 		adc_clk,
8         output reg	adc_cs_n,
9         output reg	[7:0]adc_data
10     );
11 	
12 	reg	[7:0] adc_data_buf;
13 	reg	[3:0] cnt;
14 	reg adc_clk_valid;
15 	reg adc_cs_n_valid;
16 
17     reg clk_1m;
18     reg [31:0]counter_1m;
19     always @(posedge clk) begin
20         if (counter_1m == 0) begin
21             counter_1m <= SPEED;
22             clk_1m <= ~clk_1m;
23         end else begin
24             counter_1m <= counter_1m - 1;
25         end
26     end
27 
28     reg clk_40k;
29     reg [31:0]counter_40k;
30     always @(posedge clk_1m) begin
31         if (counter_40k == 0) begin
32             counter_40k <= 12;
33             clk_40k <= ~clk_40k;
34         end else begin
35             counter_40k <= counter_40k - 1;
36         end
37     end
38 
39 	always @(posedge clk_1m) begin
40 		if(clk_40k == 0) begin
41 			cnt <= 0;
42 		end else if(cnt == 10) begin
43 			cnt <= 10;
44 		end else begin
45 			cnt <= cnt + 1'b1;
46         end
47 		adc_clk_valid <= !((cnt == 0) | (cnt == 1) | (cnt == 10));
48 		adc_cs_n <= (cnt == 0) | (cnt == 10);
49     end
50 	
51 	assign adc_clk = adc_clk_valid ? clk_1m : 1'b0;
52 
53 	always @(posedge adc_clk) begin
54 		if(adc_cs_n == 0) begin
55 			adc_data_buf <= {adc_data_in, adc_data_buf[7:1]};
56         end
57     end
58 
59 	always @(posedge clk_40k) begin
60 		adc_data <= adc_data_buf;
61     end
62 		
63 endmodule