Module: interface_uart

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Source

2 module interface_uart
3     #(parameter BUFFER_SIZE=80, parameter MSGID=32'h74697277, parameter TIMEOUT=32'd4800000, parameter ClkFrequency=12000000, parameter Baud=2000000)
4     (
5         input clk,
6         output reg [BUFFER_SIZE-1:0] rx_data,
7         input [BUFFER_SIZE-1:0] tx_data,
8         output UART_TX,
9         input UART_RX
10     );
11 
12     reg [BUFFER_SIZE-1:0] tx_data_buffer;
13     reg [BUFFER_SIZE-1:0] rx_data_buffer;
14 
15     reg TxD_start = 0;
16     wire TxD_busy;
17 
18     reg [7:0] TxD_data;
19     wire [7:0] RxD_data;
20     wire RxD_data_ready;
21     wire RxD_idle;
22     wire RxD_endofpacket;
23 
24     uart_rx #(ClkFrequency, Baud) uart_rx1 (
25         .clk (clk),
26         .RxD (UART_RX),
27         .RxD_data_ready (RxD_data_ready),
28         .RxD_data (RxD_data),
29         .RxD_idle (RxD_idle),
30         .RxD_endofpacket (RxD_endofpacket)
31     );
32 
33     uart_tx #(ClkFrequency, Baud) uart_tx1 (
34         .clk (clk),
35         .TxD_start (TxD_start),
36         .TxD_data (TxD_data),
37         .TxD (UART_TX),
38         .TxD_busy (TxD_busy)
39     );
40 
41     reg tx_state = 0;
42     reg [7:0] rx_counter = 0;
43     reg [7:0] tx_counter = 0;
44 
45     always @(posedge clk) begin
46         if (RxD_endofpacket == 1) begin
47             rx_counter <= 0;
48         end else if (tx_state == 1) begin
49             if (TxD_busy == 0) begin
50                 TxD_data <= tx_data_buffer[BUFFER_SIZE-1:BUFFER_SIZE-1-7];
51                 TxD_start <= 1;
52             end else if (TxD_start == 1) begin
53                 TxD_start <= 0;
54                 if (tx_counter < BUFFER_SIZE/8-1) begin
55                     tx_counter <= tx_counter+1;
56                     tx_data_buffer <= {tx_data_buffer[BUFFER_SIZE-1-8:0], 8'd0};
57                 end else begin
58                     tx_state <= 0;
59                 end
60             end
61         end else if (RxD_data_ready == 1) begin
62             if (rx_counter < BUFFER_SIZE/8-1) begin
63                 rx_data_buffer <= {rx_data_buffer[BUFFER_SIZE-1-8:0], RxD_data};
64                 rx_counter <= rx_counter + 1;
65             end else begin
66                 // TODO: check MSGID
67                 rx_data <= {rx_data_buffer[BUFFER_SIZE-1-8:0], RxD_data};
68                 rx_counter <= 0;
69                 tx_counter <= 0;
70                 tx_data_buffer <= tx_data;
71                 tx_state <= 1;
72             end
73         end
74     end
75 endmodule