Module: pll

Filename: pll.v

Ports:

Direction	Size	Name
output		locked
output		sysclk
input		sysclk_in

Parameter:

Parameter	Default
DIVISOR	0000000000000000000000000010

Child-Modules

Source


module pll(
        input sysclk_in,
        output reg sysclk,
        output reg locked
    );

    reg[27:0] counter=28'd0;
    parameter DIVISOR = 28'd2;
    always @(posedge sysclk_in) begin
        counter <= counter + 28'd1;
        if(counter>=(DIVISOR-1)) begin
            counter <= 28'd0;
        end
        sysclk <= (counter